10 reasons why selecting Tiempo innovative IPs and design technology
Our asynchronous IPs consumes power only where and when needed. As a result, the power consumption of our IP blocks is 4 to 5 times lower than equivalent clocked systems. Moreover, by switching to a clockless design for some block, one can remove some power-consuming blocks (e.g. PLLs) which are not needed anymore.
Tiempo clockless IPs can be integrated very quickly into any design:
- Tiempo IPs do not require timing constraints to be met to guarantee functional correctness and can then be inserted very simply into any design
- Tiempo IPs are delivered with asynchronous to synchronous interfaces which allow easy integration of Tiempo IPs into an existing synchronous system
- Clockless blocks are very well suited for modular designs as the delay insensitivity and the absence of clock drastically simplify their integration in particular regarding back-end steps and power management
- Asynchronous blocks are easy to place and route as complex clock trees are nonexistent as well as set-up/hold timing requirements
Tiempo clockless IPs are very robust against hardware attacks and are very well suited for security demanding applications.
Thank to low-level "request-acknowledge" protocol and data encoding, Tiempo IP block can be 100% resistant to physical perturbation attacks (like light flash manipulation). This can be achieved with very low overhead in gate count.
The removal of the traditional clock signal which is not found in Tiempo asynchronous designs can also be very effective to harden the resistance of a chip against side-channel attacks. One can indeed observe that the current profile of such ICs is much flatter.
As stated by Brightsight, a well-established and independent lab who conducted a preliminary study, "Tiempo asynchronous technology is very likely to increase resistance against power analysis and perturbation attacks".
Tiempo clockless IP are functionally correct, regardless of the delay in the gates and wires in the chip. As a result, chips (or parts of) designed with our clockless technology will work with a wide dynamic voltage range. This would allow for example to directly power a chip with an RF antenna (or a solar panel) without any regulation on the voltage.
This property can also be used to always work at optimum power. Depending on the required processing speed, one can lower input voltage to slow the block and reduce even more power consumption.
Tiempo clockless designs are very well suited for advanced technology nodes. Such design is locally self-adaptive to PVT variations ensuring the correctness of the block by construction. Furthermore, the removal of complex clock constraints (especially on advanced technology nodes) will considerably ease the design of complex systems.
Overall one can expect a higher yield with Tiempo clockless design technology because PVT variations do no affect the functionality of Tiempo circuits.
Tiempo clockless IPs are always working at the optimum speed offered by the circuit structure and technology. Whenever a combinational computation between two clock ticks is slow, traditional clocked circuits need to align all the circuit on this bottleneck computation estimated in worst case condition. This is very inefficient as all the other parts of the circuits could perform faster and the actual working conditions are never the worst.
Using Tiempo clockless technology, computation are processed based on a request/acknowledge mechanism. As a result, although some computation might be slow, if the majority of them can be fast, the overall circuit will perform much faster.
Integrating Tiempo clockless IPs is very simple and so is the design of new asynchronous blocks.
- Tiempo clockless IPs are always delivered with a synchronous to asynchronous interface which allows seamless integration of our block within clocked designs
- Tiempo IPs are described in a standard language, SystemVerilog, allowing to simulate these IPs with any existing simulation tool
- Tiempo IPs are modeled using SystemVerilog, a language with a high level of abstraction which is easy to understand and to learn
- Tiempo IPs are not subject to local clock constraints (e.g. setup & hold timings) therefore they can be very easily inserted into any design
- Back-end design is also much faster as the constraints on Tiempo blocks are quite limited
Tiempo can fully engage on the performance of its asynchronous IPs, in terms of electrical characteristics, speed and timing. Our team of expert designers will assist you in finding the best way to get the maximum benefits from our clockless design technology. We will also train your team to our IPs and coding style, so that you can further use our synthesis tool to make your very own clockless blocks. We are dedicated to your success!
Tiempo IPs are by default in sleep mode and can resume in a few nanoseconds, as no clock generation is needed during this process. The reason is that Tiempo delay insensitive and asynchronous designs are based on a local "request/acknowledge" protocol. When the chip is not operating it is simply "waiting" for the next request and is ready to process it. As a result, wake-up is 1000 times faster than clocked systems.
This is very well suited for chips (or part of) which need to be up and running before the rest of the system, such as power-management blocks, as well as for application requiring ultra-fast reaction as found in some safety devices.
In our clockless systems, computations are not any more aligned with regular clock edges patterns but rather spread in time. As a result, the current profile of such IP blocks is very flat. This property is very important for secured systems, but also for RF communication systems sensitive to the retro-modulation phenomenum.
Furthermore, such a low current profile leads to very low EMI (Electromagnetic Interference). This is very important in aeronautic, automotive or medical applications