Design Services
Overview
We can offer several design services:
IP customization: Our IPs are fully packaged and delivered with asynchronous to synchronous interfaces enabling a seamless integration into existing SoC architectures. Additionally, it is possible to customize our IPs to match specificities of your design such as interfaces, additional functionalities, custom instruction set for TAM16 etc.
Design evaluation: We offer consulting services to evaluate the benefit of our clockless design technology on your circuit. We can evaluate the estimated power gain and speed of a block ported to an asynchronous implementation at a block level but also from a system perspective where the removal of unnecessary PLLs could save a lot of power and area.
Custom design: We can implement a new block in asynchronous design and estimate very early in the design process the performance in speed and power consumption. Should you have a block that you believe would benefit from a clockless implementation, we can deliver a SystemVerilog clockless IP matching your existing block.
Benefits
- Evaluate the benefits of our clockless design technology on your own design, on a block by block basis
- Customize one of our existing IPs to match your very specific needs and interfaces
- Get involved in the design of a first asynchronous block to become knowledgeable about our design methodology
- Speed-up the time-to-market of your asynchronous design
