ACC: Asynchronous Circuit Compiler
Overview
ACC (Asynchronous Circuit Compiler) is the first synthesis tool which automatically generates asynchronous and delay-insensitive circuits from a model written in a standard hardware description language.
ACC takes as input a description written in SystemVerilog, which is perfectly suited for high-level modeling of clockless circuits, and generates as output a gate-level netlist in standard Verilog format. ACC can be inserted in any standard design flow, allowing designer to verify asynchronous and mixed asynchronous/synchronous circuits using any industry-standard simulation tools. The generated Verilog netlist can then be placed-and-routed using any standard back-end tool and verified with any electrical simulation tool.
ACC is available as an optional license attached to any Tiempo core IP license, allowing customers to independently modify the purchased IPs as well as to synthesize their specific asynchronous blocks complementing these IPs.
Tiempo design flow for mixed asynchronous/synchronous circuits
Features
- Fully automated synthesis tool
- Standard hardware description languages
- Input: SystemVerilog TLM-like model
- Output: Verilog gate-level netlist
- Fully integrated in standard EDA flows
- Tool license attached to IP license (option)
