News
Apr 2013: French consortium announces development of a clockless smartcard chip
- Tiempo, expert in the design of secured clockless chips, has initiated the collaborative project ASMART with CEA-LETI, Gemalto, Invia, LFoundry Rousset and Presto Engineering to develop an innovative smartcard chip prototype based on Tiempo secured clockless platform.
- Read the full press release here
Jun 2012: Tiempo announces silicon validation of TESIC, Tiempo secured platform
- Tiempo, expert in the design of advanced secured chips, today announced it has proven on silicon its secured transaction platform, TESIC, manufactured on TSMC 130 nm LP process.
- Read the full press release here
Jun 2012: Tiempo, working with STMicroelectronics, unveils first 32nm clockless test chip
- Tiempo, working closely with STMicroelectronics, announced the first fully clockless and delay-insensitive circuit in 32nm. The chip was fabricated as first-time-right silicon, with all chip samples 100% functional.
- Asynchronous circuit demonstrates unprecedented robustness to process variation on 32nm technology, paving the way for first-time-right silicon for advanced process nodes
- Read the full press release here
Apr 2012: Tiempo and Alcinéo announce partnership for smartcard applications
- Tiempo and Alcinéo, specialist in secure payment solutions, have signed an agreement to develop smartcard applications on Tiempo prototype platform.
- Read full press release here
Dec 2011: Tiempo releases FPGA emulator and SDK of TESIC secure platform
Tiempo announces the release of the preliminary version of TESIC, its highly secure, high speed embedde secure platform. This first release is an evaluation kit containing an FPGA-based emulator with a complete SDK for software development.
- Xilinx virtex6 FPGA emulating Tiempo clockless secure platform
- Full SDK tool chain available
- Complete set of software libraries included
- Contact Tiempo for more information

