Cryptoprocessors IP cores: AES
Tiempo AES IP core offers an unmatched performance over power consumption ratio. Operating at a wide and variable voltage range, this core enable very fast transaction for embedded applications. It is also highly secured against attacks thanks to its asynchronous implementation.
Key benefits
AES block-diagram
- Ultra-low power consumption
- Ultra-low current peaks
- Work at low and variable voltage
- Resistant to power and fault attacks
Key Features
- Fast execution of standard AES ciphering and deciphering algorithms
- Fully asynchronous and delay insensitive
- Available as Verilog netlist[1] ready for P&R
- Optional: Verilog netlist[1] secured against hardware attacks
- Optional: Verilog netlist[1] strengthened for ultra-low noise and ultra low EMI
Applications
Targeted applications are chips for smartcards (with or without contact), RFID, tags, systems embedding NFC technology and other secured applications.
Electrical characteristics
Figures below are based on electrical simulations on TSCM130LP 1.5V process after Place & Route. Simulations are run on the secured version of the IP.
| Supply voltage range | 1.0V | 1.5V |
|---|---|---|
| AES Ciphering average current consumption | 360 µA | 1.6 mA |
| AES Ciphering time | 11.53 µs | 4 µs |
| AES Deciphering average current consumption | 370 µA | 1.61 mA |
| AES Deciphering time | 17.83 µs | 6.14 µs |
[1]Please contact Tiempo for available libraries and technologies